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| Quad, 14-bit, 50 MSPS Serial LVDS 1.8 V A/D Converter AD9259 FEATURES Four ADCs integrated into 1 package 98 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = 0.5 LSB (typical) INL = 1.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 315 MHz full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9259 VIN + A VIN - A VIN + B VIN - B VIN + C VIN - C VIN + D VIN - D VREF SENSE REFT REFB REF SELECT T/H PIPELINE ADC 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS D+A D-A D+B D-B D+C D-C D+D D-D T/H PIPELINE ADC PIPELINE ADC PIPELINE ADC T/H T/H + - FCO+ 0.5V SERIAL PORT INTERFACE DATA RATE MULTIPLIER FCO- DCO+ DCO- 05965-001 RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK- Figure 1. APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI(R)). The AD9259 is available in a Pb-free, 48-lead LFCSP package. It is specified over the industrial temperature range of -40C to +85C. GENERAL DESCRIPTION The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Small Footprint. Four ADCs are contained in a small, spacesaving package; low power of 98 mW/channel at 50 MSPS. Ease of Use. A data clock output (DCO) operates up to 350 MHz and supports double data rate operation (DDR). User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9228 (12-bit). One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. AD9259 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams.............................................................................. 7 Absolute Maximum Ratings............................................................ 9 Thermal Impedance ..................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 14 Theory of Operation ...................................................................... 18 Analog Input Considerations ................................................... 18 Clock Input Considerations...................................................... 20 Serial Port Interface (SPI).............................................................. 28 Hardware Interface..................................................................... 28 Memory Map .................................................................................. 30 Reading the Memory Map Table.............................................. 30 Reserved Locations .................................................................... 30 Default Values ............................................................................. 30 Logic Levels................................................................................. 30 Evaluation Board ............................................................................ 34 Power Supplies ............................................................................ 34 Input Signals................................................................................ 34 Output Signals ............................................................................ 34 Default Operation and Jumper Selection Settings................. 35 Alternative Analog Input Drive Configuration...................... 36 Outline Dimensions ....................................................................... 50 Ordering Guide .......................................................................... 50 REVISION HISTORY 6/06--Revision 0: Initial Version Rev. 0 | Page 2 of 52 AD9259 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3 1 2 Temperature Min 14 AD9259-50 Typ Max Unit Bits Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.7 1.7 Guaranteed 1 2 0.5 0.3 0.5 1.5 2 17 21 5 3 6 2 AVDD/2 7 315 1.8 1.8 185 32.5 392 2 72 -100 -100 8 8 2 0.7 1.0 3.5 mV mV % FS % FS LSB LSB ppm/C ppm/C ppm/C 30 mV mV k V p-p V pF MHz 1.9 1.9 192.5 34.7 409 4 V V mA mA mW mW mW dB dB See the AN-835 Application Note, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed. Can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. Rev. 0 | Page 3 of 52 AD9259 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Min AD9259-50 Typ Max 73.5 71.0 73.0 72.8 72.7 70.2 72.2 72.0 12.0 11.6 11.9 11.9 84 73 84 78 -88 -84 -73 -78 -90 -90 -80 -88 80.0 80.0 Unit dB dB dB dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) EFFECTIVE NUMBER OF BITS (ENOB) SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST HARMONIC (Second or Third) WORST OTHER (Excluding Second or Third) TWO-TONE INTERMODULATION DISTORTION (IMD)-- AIN1 AND AIN2 = -7.0 dBFS fIN = 2.4 MHz fIN = 19.7 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 70 MHz fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz 1 See the AN-835 Application Note, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 52 AD9259 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) Logic 1 Voltage (IOH = 50 A) Logic 0 Voltage (IOL = 50 A) DIGITAL OUTPUTS (D+, D-), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D-), (Low Power, Reduced Signal Option)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 Temperature Min AD9259-50 Typ Max CMOS/LVDS/LVPECL Unit Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3 mV p-p V k pF V V k pF V V k pF V V k pF V V Full Full 247 1.125 454 1.375 Offset binary mV V LVDS Full Full 150 1.10 250 1.30 Offset binary mV V See the AN-835 Application Note, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only. Rev. 0 | Page 5 of 52 AD9259 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 4. Parameter 1 CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 3 DCO to Data Delay (tDATA)3 DCO to FCO Delay (tFRAME)3 Data to Data Skew (tDATA-MAX - tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time 1 2 Temp Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Full Min 50 AD9259-50 Typ Max Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns s CLK cycles ps ps rms CLK cycles 10 10 10 2.0 2.7 300 300 2.7 tFCO + (tSAMPLE/28) (tSAMPLE/28) (tSAMPLE/28) 50 600 375 10 3.5 2.0 3.5 (tSAMPLE/28) - 300 (tSAMPLE/28) - 300 (tSAMPLE/28) + 300 (tSAMPLE/28) + 300 150 25C 25C 25C 500 <1 2 See the AN-835 Application Note, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed. Can be adjusted via the SPI interface. 3 tSAMPLE/28 is based on the number of bits multiplied by 2; delays are based on half duty cycles. Rev. 0 | Page 6 of 52 AD9259 TIMING DIAGRAMS N-1 AIN tA N CLK- tEH tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD D- MSB N - 10 D+ D12 N - 10 D11 N - 10 D10 N - 10 D9 N - 10 tDATA 05965-039 D8 N - 10 D7 N - 10 D6 N - 10 D5 N - 10 D4 N - 10 D3 N - 10 D2 N - 10 D1 N - 10 D0 N - 10 MSB N-9 D12 N-9 Figure 2. 14-Bit Data Serial Stream (Default) N-1 AIN tA N CLK- tEH tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD D- MSB N - 10 D10 N - 10 D9 N - 10 D8 N - 10 D7 N - 10 tDATA D6 N - 10 D5 N - 10 D4 N - 10 D3 N - 10 D2 N - 10 D1 N - 10 D0 N - 10 MSB N-9 D10 N-9 D+ Figure 3. 12-Bit Data Serial Stream Rev. 0 | Page 7 of 52 05965-040 AD9259 N-1 AIN tA N tEH CLK- tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD D- LSB N - 10 D+ D0 N - 10 D1 N - 10 D2 N - 10 D3 N - 10 tDATA 05965-041 D4 N - 10 D5 N - 10 D6 N - 10 D7 N - 10 D8 N - 10 D9 N - 10 D10 N - 10 D11 N - 10 D12 N - 10 LSB N-9 D0 N-9 Figure 4. 14-Bit Data Serial Stream, LSB First Rev. 0 | Page 8 of 52 AD9259 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D+, D-, DCO+, DCO-, FCO+, FCO-) CLK+, CLK- VIN+, VIN- SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To AGND DRGND DRGND DRVDD DRGND Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +2.0 V -0.3 V to +2.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 6. Air Flow Velocity (m/s) 0.0 1.0 2.5 1 AGND AGND AGND AGND AGND AGND -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -40C to +85C 150C 300C -65C to +150C JA1 24C/W 21C/W 19C/W JB 12.6C/W JC 1.2C/W JA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 52 AD9259 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN - C VIN + C VIN + B 38 48 47 46 45 44 43 42 41 40 39 37 AVDD 1 AVDD 2 VIN - D 3 VIN + D 4 AVDD 5 AVDD 6 CLK- 7 CLK+ 8 AVDD 9 AVDD 10 DRGND 11 DRVDD 12 13 PIN 1 INDICATOR VIN - B SENSE RBIAS AVDD AVDD AVDD REFB VREF REFT 36 35 34 AVDD AVDD VIN - A VIN + A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) 33 32 AD9259 31 30 29 28 27 26 25 TOP VIEW D + D 14 15 D + C 16 17 D + A 20 21 FCO+ 22 23 DCO+ 24 D + B 18 D - A 19 Figure 5. 48-Lead LFCSP Top View Table 7. Pin Function Descriptions Pin No. 0 1, 2, 5, 6, 9, 10, 27, 32, 35, 36, 39, 45, 46 11, 26 12, 25 3 4 7 8 13 14 15 16 17 18 19 20 21 22 23 24 28 29 30 31 33 34 Name AGND AVDD DRGND DRVDD VIN - D VIN + D CLK- CLK+ D-D D+D D-C D+C D-B D+B D-A D+A FCO- FCO+ DCO- DCO+ SCLK/DTP SDIO/ODM CSB PDWN VIN + A VIN - A Description Analog Ground (Exposed Paddle) 1.8 V Analog Supply Digital Output Driver Ground 1.8 V Digital Output Driver Supply ADC D Analog Input--Complement ADC D Analog Input--True Input Clock--Complement Input Clock--True ADC D Complement Digital Output ADC D True Digital Output ADC C Complement Digital Output ADC C True Digital Output ADC B Complement Digital Output ADC B True Digital Output ADC A Complement Digital Output ADC A True Digital Output Frame Clock Output--Complement Frame Clock Output--True Data Clock Output--Complement Data Clock Output--True Serial Clock/Digital Test Pattern Serial Data Input-Output/Output Driver Mode CSB Power-Down ADC A Analog Input--True ADC A Analog Input--Complement Rev. 0 | Page 10 of 52 05965-003 FCO- D-D D-C D-B DCO- AD9259 Pin No. 37 38 40 41 42 43 44 47 48 Name VIN - B VIN + B RBIAS SENSE VREF REFB REFT VIN + C VIN - C Description ADC B Analog Input--Complement ADC B Analog Input--True External Resistor Sets the Internal ADC Core Bias Current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) ADC C Analog Input--True ADC C Analog Input--Complement Rev. 0 | Page 11 of 52 AD9259 EQUIVALENT CIRCUITS DRVDD V V D+ V VIN D- V 05965-030 DRGND Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent Digital Output Circuit 10 CLK 10k 1.25V 10k 10 CLK SCLK/PDWN 1k 30k 05965-032 05965-005 Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/PDWN Input Circuit RBIAS 100 SDIO/ODM 350 05965-035 Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit Rev. 0 | Page 12 of 52 05965-031 30k 05965-033 AD9259 AVDD 70k CSB 1k VREF 05965-034 6k Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit SENSE 1k Figure 13. Equivalent SENSE Circuit 05965-036 Rev. 0 | Page 13 of 52 05965-037 AD9259 TYPICAL PERFORMANCE CHARACTERISTICS 0 AIN = -0.5dBFS SNR = 73.8dB ENOB = 11.88 BITS SFDR = 83.4dBc AMPLITUDE (dBFS) 0 AIN = -0.5dBFS SNR = 67.31dB ENOB = 10.89 BITS SFDR = 77.38dBc -20 -20 AMPLITUDE (dBFS) -40 -40 -60 -60 -80 -80 -100 -100 05965-052 0 5 10 15 FREQUENCY (MHz) 20 25 0 5 10 15 20 25 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 18. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 50 MSPS 0 AIN = -0.5dBFS SNR = 72.94dB ENOB = 11.57 BITS SFDR = 78.60dBc AMPLITUDE (dBFS) 0 AIN = -0.5dBFS SNR = 66.87dB ENOB = 10.82 BITS SFDR = 74.97dBc -20 -20 AMPLITUDE (dBFS) -40 -40 -60 -60 -80 -80 -100 -100 05965-085 0 5 10 15 FREQUENCY (MHz) 20 25 0 5 10 15 20 25 FREQUENCY (MHz) Figure 16. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 50 MSPS Figure 19. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 50 MSPS 0 AIN = -0.5dBFS SNR = 71.96dB ENOB = 11.41 BITS SFDR = 76.68dBc AMPLITUDE (dBFS) 0 AIN = -0.5dBFS SNR = 65.62dB ENOB = 10.61 BITS SFDR = 68.11dBc -20 -20 AMPLITUDE (dBFS) -40 -40 -60 -60 -80 -80 -100 -100 05965-053 0 5 10 15 FREQUENCY (MHz) 20 25 0 5 10 15 20 25 FREQUENCY (MHz) Figure 17. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 50 MSPS Rev. 0 | Page 14 of 52 Figure 20. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 50 MSPS 05965-050 -120 -120 05965-051 -120 -120 05965-054 -120 -120 AD9259 90 2V p-p, SFDR 100 90 85 fIN = 35MHz fSAMPLE = 50MSPS 2V p-p, SFDR 80 70 SNR/SFDR (dB) SNR/SFDR (dB) 80 60 50 40 30 20 10 80dB REFERENCE 2V p-p, SNR 75 2V p-p, SNR 70 65 05965-059 15 20 25 30 35 ENCODE (MSPS) 40 45 50 -50 -40 -30 -20 -10 0 ANALOG INPUT LEVEL (dBFS) Figure 21. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 50 MSPS Figure 24. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 50 MSPS 90 0 AIN1 AND AIN2 = -7dBFS SFDR = 87.76dBc IMD2 = 90.18dBc IMD3 = 87.27dBc 85 2V p-p, SFDR -20 AMPLITUDE (dBFS) SNR/SFDR (dB) 80 -40 75 -60 70 2V p-p, SNR -80 65 -100 05965-060 15 20 25 30 35 ENCODE (MSPS) 40 45 50 0 5 10 15 20 25 FREQUENCY (MHz) Figure 22. SNR/SFDR vs. fSAMPLE, fIN = 35 MHz, fSAMPLE = 50 MSPS Figure 25. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 50 MSPS 100 90 80 AMPLITUDE (dBFS) 0 fIN = 10.3MHz fSAMPLE = 50MSPS 2V p-p, SFDR -20 AIN1 AND AIN2 = -7dBFS SFDR = 80.37dBc IMD2 = 79.75dBc IMD3 = 84.50dBc 70 SNR/SFDR (dB) -40 60 50 40 30 20 10 05965-066 2V p-p, SNR -60 -80 80dB REFERENCE -100 -50 -40 -30 -20 -10 0 0 5 10 15 20 25 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 23. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS Figure 26. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 50 MSPS Rev. 0 | Page 15 of 52 05965-055 0 -60 -120 05965-056 60 10 -120 05965-065 60 10 0 -60 AD9259 90 85 2V p-p, SFDR (dBc) 80 0.5 0.4 0.3 0.2 SNR/SFDR (dB) 70 65 60 2V p-p, SNR (dB) DNL (LSB) 75 0.1 0 -0.1 -0.2 -0.3 55 50 -0.4 05965-071 1 10 100 1000 0 2000 4000 6000 ANALOG INPUT FREQUENCY (MHz) 8000 10000 12000 14000 16000 CODE Figure 27. SNR/SFDR vs. fIN, fSAMPLE = 50 MSPS Figure 30. DNL, fIN = 2.4 MHz, fSAMPLE = 50 MSPS 90 -30 -35 2V p-p, SFDR -40 85 SINAD/SFDR (dB) 80 CMRR (dB) -45 -50 -55 -60 75 70 2V p-p, SINAD 65 05965-072 60 -40 -20 0 20 40 60 80 -70 0 5 10 15 20 25 30 35 TEMPERATURE (C) FREQUENCY (MHz) Figure 28. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 50 MSPS Figure 31. CMRR vs. Frequency, fSAMPLE = 50 MSPS 2.0 1.5 1.0 0.5 NUMBER OF HITS (Millions) 1.2 1.006 LSB rms 1.0 0.8 INL (LSB) 0 -0.5 -1.0 -1.5 -2.0 0.6 0.4 0.2 05965-086 05965-073 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE 0 N-3 N-2 N-1 N CODE N+1 N+2 N+3 Figure 29. INL, fIN = 2.4 MHz, fSAMPLE = 50 MSPS Figure 32. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS Rev. 0 | Page 16 of 52 05965-075 -65 05965-074 -0.5 AD9259 0 NPR = 63.89dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz FUNDAMENTAL LEVEL (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 0 5 10 15 20 25 05965-076 -20 AMPLITUDE (dBFS) -3dB CUTOFF = 315MHz -40 -60 -80 -100 -120 -10 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. Noise Power Ratio (NPR), fSAMPLE = 50 MSPS Figure 34. Full Power Bandwidth vs. Frequency, fSAMPLE = 50 MSPS Rev. 0 | Page 17 of 52 05965-077 AD9259 THEORY OF OPERATION The AD9259 architecture consists of a pipelined ADC that is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock. SNR/SFDR (dB) low-Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit any unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article "Transformer-Coupled Front-End for Wideband A/D Converters" for more information on this subject. In general, the precise values depend on the application. The analog inputs of the AD9259 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 36 and Figure 37. 90 85 80 75 70 65 60 55 50 0.2 SNR (dB) fIN = 2.3MHz fSAMPLE = 50MSPS SFDR (dBc) ANALOG INPUT CONSIDERATIONS The analog input to the AD9259 is a differential switched-capacitor circuit designed for processing differential input signals. The input can support a wide common-mode range and maintain excellent performance. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) H CPAR VIN+ CSAMPLE S S CSAMPLE VIN- CPAR H SNR/SFDR (dB) Figure 36. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, fSAMPLE = 50 MSPS H S S 80 90 85 fIN = 30MHz fSAMPLE = 50MSPS SFDR (dBc) H 05965-006 75 70 65 60 55 50 0.2 SNR (dB) Figure 35. Switched-Capacitor Input Circuit The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 35). When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce the high differential capacitance seen at the analog inputs, thus realizing the maximum bandwidth of the ADC. Such use of Rev. 0 | Page 18 of 52 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 37. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 50 MSPS 05965-079 0.4 0.6 0.8 1.0 1.2 1.4 1.6 05965-078 AD9259 For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. Maximum SNR performance is always achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9259, the largest input span available is 2 V p-p. ADT1-1WT 1:1 Z RATIO R C VIN+ 2V p-p 49.9 AVDD 1k 1k 0.1F 1C DIFF ADC AD9259 VIN- AGND R C 1C DIFF IS OPTIONAL. Figure 38. Differential Transformer Coupled Configuration for Baseband Applications 2V p-p 16nH 65 ADT1-1WT 0.1F 1:1 Z RATIO 16nH 499 16nH AVDD 1k 1k 0.1F 05965-047 33 2.2pF 33 1k VIN+ ADC AD9259 VIN- Figure 39. Differential Transformer Coupled Configuration for IF Applications Differential Input Configurations There are several ways in which to drive the AD9259 either actively or passively. In either case, the optimum performance is achieved by driving the analog input differentially. One example is by using the AD8332 differential driver. It provides excellent performance and a flexible interface to the ADC (see Figure 41) for baseband applications. This configuration is common for medical ultrasound systems. However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9259. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. Two examples are shown in Figure 38 and Figure 39. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can still be applied to the ADC's VIN+ pin while the VIN- pin is terminated. Figure 40 details a typical single-ended input configuration. AVDD C R 2V p-p 49.9 0.1F 1k AVDD 1k 25 0.1F 1k 1C DIFF VIN+ ADC AD9259 VIN- R C 1C DIFF IS OPTIONAL. Figure 40. Single-Ended Input Configuration 0.1F LOP 0.1F 120nH 1V p-p 22pF VIP VOH 187 0.1F 1.0k VGA 374 1.0k R C R INH AD8332 LNA LMD VIN+ ADC AD9259 VIN- 10F 05965-007 0.1F VOL LON VIN 187 VREF 0.1F 0.1F 18nF 274 0.1F Figure 41. Differential Input Configuration Using the AD8332 Rev. 0 | Page 19 of 52 05965-009 05965-008 AD9259 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9259 sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 42 shows one preferred method for clocking the AD9259. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9259 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9259 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. MIN-CIRCUITS ADT1-1WT, 1:1Z 0.1F XFMR 100 0.1F 0.1F SCHOTTKY DIODES: HSM2812 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 45). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLK 501 CMOS DRIVER CLK 0.1F 0.1F 150 RESISTOR IS OPTIONAL. 0.1F CLOCK INPUT OPTIONAL 0.1F 100 CLK+ ADC AD9259 CLK- 05965-027 39k 0.1F CLOCK INPUT 50 Figure 45. Single-Ended 1.8 V CMOS Sample Clock CLK+ ADC AD9259 05965-024 CLK- CLOCK INPUT 0.1F 501 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLK OPTIONAL 0.1F 100 CMOS DRIVER CLK CLK+ Figure 42. Transformer Coupled Differential Clock 0.1F 0.1F ADC AD9259 05965-028 If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 43. The AD9510/AD9511/AD9512/AD9513/AD9514/ AD9515 family of clock drivers offers excellent jitter performance. AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1F CLK PECL DRIVER CLK 501 501 240 240 05965-025 CLK- 150 RESISTOR IS OPTIONAL. Figure 46. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9259 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9259. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 10 clock cycles to allow the DLL to acquire and lock to the new rate. CLOCK INPUT 0.1F CLK+ 100 0.1F CLOCK INPUT 0.1F ADC AD9259 CLK- 150 RESISTORS ARE OPTIONAL. Figure 43. Differential PECL Sample Clock AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1F CLK LVDS DRIVER CLK 50* 501 05965-026 CLOCK INPUT 0.1F CLK+ 100 0.1F CLOCK INPUT 0.1F ADC AD9259 CLK- 150 RESISTORS ARE OPTIONAL Figure 44. Differential LVDS Sample Clock Rev. 0 | Page 20 of 52 AD9259 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR degradation = 20 x log 10 [1/2 x x fA x tJ] In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 47). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9259. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit www.analog.com). 130 120 110 100 SNR (dB) Power Dissipation and Power-Down Mode As shown in Figure 48, the power dissipated by the AD9259 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 200 180 160 140 AVDD CURRENT 450 500 CURRENT (mA) 120 100 80 60 40 20 10 15 20 25 30 35 40 45 50 DRVDD CURRENT TOTAL POWER 400 350 300 ENCODE (MSPS) Figure 48. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS RMS CLOCK JITTER REQUIREMENT 16 BITS 14 BITS 12 BITS 10 BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 1 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 05965-038 90 80 70 60 50 40 30 Figure 47. Ideal SNR vs. Input Frequency and Jitter Rev. 0 | Page 21 of 52 05965-089 0 250 POWER (mW) AD9259 By asserting the PDWN pin high, the AD9259 is placed in power-down mode. In this state, the ADC typically dissipates 2 mW. During power-down, the LVDS output drivers are placed in a high impedance state. The AD9259 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 2.2 F decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 375 s to restore full operation. There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features. 100 termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. An example of the FCO and data stream with proper trace length and position can be found in Figure 49. Figure 49. LVDS Output Timing Example in ANSI Mode (Default) Digital Outputs and Timing The AD9259 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SDIO/ODM pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 17 mW. See the SDIO/ODM Pin section or Table 15 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9259 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 50. Figure 51 shows an example of when the trace lengths exceed 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all four outputs in order to drive longer trace lengths (see Figure 52). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. Also notice in Figure 52 that the histogram has improved. See the Memory Map section for more details. Rev. 0 | Page 22 of 52 05965-045 CH1 500mV/DIV = DCO CH2 500mV/DIV = DATA CH3 500mV/DIV = FCO 2.5ns/DIV AD9259 500 EYE DIAGRAM VOLTAGE (V) EYE: ALL BITS ULS: 10000/15600 EYE DIAGRAM VOLTAGE (V) 400 EYE: ALL BITS ULS: 9599/15599 200 0 0 -200 -400 -500 -1.0ns -0.5ns 0ns 0.5ns 1.0ns -1.0ns -0.5ns 0ns 0.5ns 1.0ns 100 TIE JITTER HISTOGRAM (Hits) 100 TIE JITTER HISTOGRAM (Hits) 50 50 05965-043 0 -100ps -0ps 100ps 0 -150ps -100ps -50ps -0ps 50ps 100ps 150ps Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less than 24 Inches on Standard FR-4 200 EYE DIAGRAM VOLTAGE (V) Figure 52. Data Eye for LVDS Outputs in ANSI Mode with 100 Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4 EYE: ALL BITS ULS: 9600/15600 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. If it is desired to change the output data format to twos complement, see the Memory Map section. Table 8. Digital Output Coding Code 16383 8192 8191 0 (VIN+) - (VIN-), Input Span = 2 V p-p (V) +1.00 0.00 -0.000122 -1.00 Digital Output Offset Binary (D11 ... D0) 11 1111 1111 1111 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0000 0 -200 -1.0ns -0.5ns 0ns 0.5ns 1.0ns 100 TIE JITTER HISTOGRAM (Hits) 50 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 14 bits times the sample clock rate, with a maximum of 700 Mbps (14 bits x 50 MSPS = 700 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up for encode rates lower than 10 MSPS via the SPI. This allows encode rates as low as 5 MSPS. See the Memory Map section to enable this feature. 0 -150ps -100ps -50ps -0ps 50ps 100ps 150ps Figure 51. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than 24 Inches on Standard FR-4 Rev. 0 | Page 23 of 52 05965-044 05965-042 AD9259 Two output clocks are provided to assist in capturing data from the AD9259. The DCO is used to clock the output data and is equal to seven times the sampling clock (CLK) rate. Data is clocked out of the AD9259 and must be captured on the rising and falling edges of the DCO that supports double data rate Table 9. Flex Output Test Modes Output Test Mode Bit Sequence 0000 0001 Subject to Data Format Select N/A Yes (DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 -Full-scale short 0100 Checker board 0101 0110 0111 PN sequence long 1 PN sequence short1 One/zero word toggle 1000 1001 User input One/zero bit toggle 1010 1x sync 1011 One bit high 1100 Mixed frequency Digital Output Word 1 N/A 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) N/A N/A 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) Register 0x19 to Register 0x1A 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) Digital Output Word 2 N/A Same Same Yes Same Yes 0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit) N/A N/A 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) Register 0x1B to Register 0x1C N/A No Yes Yes No No No N/A No N/A No N/A No 1 PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is 9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1 (short), defines the pseudorandom sequence. Rev. 0 | Page 24 of 52 AD9259 When using the serial port interface (SPI), the DCO phase can be adjusted in 60 increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO timing, as shown in Figure 2, is 90 relative to the output data edge. An 8-, 10-, and 12-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility to lower resolution systems. When changing the resolution to an 8-, 10-, or 12-bit serial stream, the data stream is shortened. See Figure 3 for a 12-bit example. When using the SPI, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is represented first in the data output serial stream (see Figure 4). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. It should be noted that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Please consult the Memory Map section for information on how to change these additional digital output timing features through the serial port interface or SPI. Table 10. Output Driver Mode Pin Settings Selected ODM Normal operation ODM ODM Voltage 10 k to AGND AVDD Resulting Output Standard ANSI-644 (default) Resulting FCO and DCO ANSI-644 (default) Low power, reduced signal option Low power, reduced signal option SCLK/DTP Pin This pin is for applications that do not require SPI mode operation. The serial clock/digital test pattern (SCLK/DTP) pin can enable a single digital test pattern if this pin and the CSB pin are held high during device power-up. When the DTP is tied to AVDD, all the ADC channel outputs shift out the following pattern: 10 0000 0000 0000. The FCO and DCO outputs still work as usual while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 k resistor. This pin is both 1.8 V and 3.3 V tolerant. Table 11. Digital Test Pattern Pin Settings Selected DTP Normal operation DTP DTP Voltage 10 k to AGND AVDD Resulting D+ and D- Normal operation 10 0000 0000 0000 Resulting FCO and DCO Normal operation Normal operation Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section to choose from the different options available. CSB Pin The chip select bar (CSB) pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. SDIO/ODM Pin This pin is for applications that do not require SPI mode operation. The SDIO/ODM pin can enable a low power, reduced signal option similar to the IEEE 1596.3 reduced range link output standard if this pin and the CSB pin are tied to AVDD during device powerup. This option should only be used when the digital output trace lengths are less than 2 inches in length to the LVDS receiver. The FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p. This output mode allows the user to further lower the power on the DRVDD supply. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 k internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 k resistor in series with this pin to limit the current. RBIAS Pin To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 k) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the ADC's AVDD current to a nominal 185 mA at 50 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. If SFDR performance is not as critical as power, simply adjust the ADC core current to achieve a lower power. Figure 53 and Figure 54 show the relationship between the dynamic range and power as the RBIAS resistance is changed. Nominally, a 10.0 k value is used, as indicated by the dashed line. Rev. 0 | Page 25 of 52 AD9259 85 83 81 79 SFDR (dBc) 77 75 73 71 69 67 2 6 10 14 18 RESISTANCE (k) 22 05965-091 80 SFDR Internal Reference Operation A comparator within the AD9259 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 55), setting VREF to 1 V. The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. If the reference of the AD9259 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 57 depicts how the internal reference voltage is affected by loading. VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB + 75 SNR 65 60 65 55 Figure 53. SFDR vs. RBIAS 600 500 SNR (dB) 70 400 IAVDD (mA) 2.2F 300 VREF 1F 0.1F SELECT LOGIC SENSE 0.5V 0.1F 200 100 Figure 54. IAVDD vs. RBIAS Figure 55. Internal Reference Configuration VIN+ VIN- REFT ADC CORE EXTERNAL REFERENCE VREF 1F1 0.1F1 AVDD SENSE SELECT LOGIC 0.5V 0.1F 0.1F REFB 0.1F + Voltage Reference A stable and accurate 0.5 V voltage reference is built into the AD9259. This is gained up by a factor of 2 internally, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9259. The recommended capacitor values and configurations for the AD9259 reference pin can be found in Figure 55. Table 12. Reference Settings Selected Mode External Reference Internal, 2 V p-p FSR SENSE Voltage AVDD AGND to 0.2 V Resulting VREF (V) N/A 1.0 Resulting Differential Span (V p-p) 2 x external reference 2.0 1OPTIONAL. 2.2F Figure 56. External Reference Operation Rev. 0 | Page 26 of 52 05965-046 05965-010 2 6 10 14 RESISTANCE (k) 18 22 05965-092 0 AD9259 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 58 shows the typical drift characteristics of the internal reference in 1 V mode. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 k load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal of 1.0 V. 5 0 -5 0.20 0.15 0.10 VREF ERROR (%) 0.05 0 -0.05 -0.10 05965-084 -0.15 -0.20 -40 -20 0 20 40 60 80 TEMPERATURE (C) Figure 58. Typical VREF Drift VREF ERROR (%) -10 -15 -20 -25 -30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) Figure 57. VREF Accuracy vs. Load 05965-083 Rev. 0 | Page 27 of 52 AD9259 SERIAL PORT INTERFACE (SPI) The AD9259 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices user manual Interfacing to High Speed ADCs via SPI. There are three pins that define the serial port interface, or SPI, to this particular ADC. They are the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 13). Table 13. Serial Port Pins Pin SCLK SDIO Function Serial Clock. The serial shift clock in. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles. In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the Serial Port Interface (SPI) section. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the user manual Interfacing to High Speed ADCs via SPI. CSB HARDWARE INTERFACE The pins described in Table 13 compose the physical interface between the user's programming device and the serial port of the AD9259. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pinstrappable functions are supported on the SPI pins. For users who simply wish to operate the DUT without using SPI, remove any connections from the CSB, SCLK/DTP, and SDIO/OMD pins. By disconnecting these pins from the control bus, the DUT can operate in its most basic operation. Each of these pins has an internal termination and will float to its respective level. The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Fields W0 and W1. An example of the serial timing and its definitions can be found in Figure 59 and Table 14. In normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. Rev. 0 | Page 28 of 52 AD9259 tDS tS CSB tHI tDH tLO tCLK tH SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON'T CARE Figure 59. Serial Timing Details Table 14. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO Timing (minimum, ns) 5 2 40 5 2 16 16 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Rev. 0 | Page 29 of 52 05965-012 AD9259 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), device index and transfer register map (Address 0x05 and Address 0xFF), and program register map (Address 0x08 to Address 0x25). The left-hand column of the memory map indicates the register address number in hexadecimal. The default value of this address is shown in hexadecimal in the right-hand column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, Clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 at this address, the duty cycle stabilizer turns off. For more information on this and other functions, consult the user manual Interfacing to High Speed ADCs via SPI. RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 15, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly, "clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit." Rev. 0 | Page 30 of 52 AD9259 Table 15. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 00 chip_port_config 0 Bit 6 LSB first 1 = on 0 = off (default) Bit 5 Soft reset 1 = on 0 = off (default) Bit 4 1 Bit 3 1 Bit 2 Soft reset 1 = on 0 = off (default) Bit 1 LSB first 1 = on 0 = off (default) Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode registers correctly regardless of shift mode. Default is unique chip ID. This is a read-only register. Child ID used to differentiate graded devices. Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation. Turns the internal duty cycle stabilizer on and off. 01 chip_id 8-bit Chip ID Bits 7:0 (AD9259 = 0x04), (default) 0x04 Read only X X X Read only 02 chip_grade X Child ID 6:4 (identify device variants of Chip ID) 100 = 50 MSPS X Clock Channel DCO 1 = on 0 = off (default) X Clock Channel FCO 1 = on 0 = off (default) X X Device Index and Transfer Registers 05 device_index_A X FF device_update X X Data Channel D 1 = on (default) 0 = off X Data Channel C 1 = on (default) 0 = off X Data Channel B 1 = on (default) 0 = off X Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F 0x00 ADC Functions 08 modes X X X X X 09 clock X X X X X Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset X X Duty cycle stabilizer 1 = on (default) 0 = off 0x00 0x01 0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Output test mode--see Table 9 in the Digital Outputs and Timing section 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = user input 1001 = one/zero bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) 0x00 When set, the test data is placed on the output pins in place of normal data. Rev. 0 | Page 31 of 52 AD9259 Addr. (Hex) 14 Parameter Name output_mode Bit 7 (MSB) X Bit 6 0 = LVDS ANSI (default) 1 = LVDS low power, (IEEE 1596.3 similar) X Bit 5 X Bit 4 X Bit 3 X Bit 2 Output invert 1 = on 0 = off (default) Bit 0 (LSB) Bit 1 00 = offset binary (default) 01 = twos complement Default Value (Hex) 0x00 Default Notes/ Comments Configures the outputs and the format of the data. 15 output_adjust X Output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100 X X X X 0x00 16 output_phase X X X X 19 1A 1B 1C 21 user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb serial_control B7 B15 B7 B15 LSB first 1 = on 0 = off (default) B6 B14 B6 B14 X B5 B13 B5 B13 X B4 B12 B4 B12 X 0011 = output clock phase adjust (0000 through 1010) (Default: 180 relative to DATA edge) 0000 = 0 relative to DATA edge 0001 = 60 relative to DATA edge 0010 = 120 relative to DATA edge 0011 = 180 relative to DATA edge 0100 = 240 relative to DATA edge 0101 = 300 relative to DATA edge 0110 = 360 relative to DATA edge 0111 = 420 relative to DATA edge 1000 = 480 relative to DATA edge 1001 = 540 relative to DATA edge 1010 = 600 relative to DATA edge 1011 to 1111 = 660 relative to DATA edge B3 B2 B1 B0 B11 B3 B11 <10 MSPS, low encode rate mode 1 = on 0 = off (default) X B10 B2 B10 B9 B1 B9 B8 B0 B8 0x03 Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 0x00 0x00 0x00 0x00 0x00 000 = 14 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSB. User-defined pattern, 2 MSB. Serial stream control. Default causes MSB first and the native bit stream (global). 22 serial_ch_stat X X X X X Channel output reset 1 = on 0 = off (default) Channel powerdown 1 = on 0 = off (default) 0x00 Used to power down individual sections of a converter (local). Rev. 0 | Page 32 of 52 AD9259 Power and Ground Recommendations When connecting power to the AD9259, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length. A single PC board ground plane should be sufficient when using the AD9259. With proper decoupling and smart partitioning of the PC board's analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the ADC is connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9259. An exposed continuous copper plane on the PCB should mate to the AD9259 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the ADC and PCB. See Figure 60 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, "A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)," at www.analog.com. SILKSCREEN PARTITION PIN 1 INDICATOR Figure 60. Typical PCB Layout Rev. 0 | Page 33 of 52 05965-013 AD9259 EVALUATION BOARD The AD9259 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a transformer (default) or through the AD8332 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8332 drive circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 63 to Figure 67). Figure 61 shows the typical bench characterization setup used to evaluate the ac performance of the AD9259. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. See Figure 63 to Figure 71 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. each section. At least one 1.8 V supply is needed with a 1 A current capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply is needed. The 5.0 V supply, or AVDD_5 V, should have a 1 A current capability. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or AVDD_3.3 V, should have a 1 A current capability as well. INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most ADI evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. ADI uses TTE, Allen Avionics, and K&L types of band-pass filters. The filter should be connected directly to the evaluation board if possible. POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Simply connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P503. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. When operating the evaluation board in a nondefault condition, L504 to L507 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for OUTPUT SIGNALS The default setup uses the HSC-ADC-FPGA high speed deserialization board to deserialize the digital output data and convert it to parallel CMOS. These two channels interface directly with the ADI standard dual-channel FIFO data capture board (HSC-ADC-EVALA-DC). Two of the four channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX SWITCHING POWER SUPPLY - 5.0V + - 1.8V + 1.8V - + - 3.3V + - 3.3V + - 1.5V + - 3.3V + 1.5V_FPGA GND GND GND GND GND GND AVDD_5V DRVDD_DUT AVDD_3.3V AVDD_DUT 3.3V_D GND VCC ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER XFMR INPUT AD9259 EVALUATION BOARD CLK SPI SPI SPI Figure 61. Evaluation Board Connection Rev. 0 | Page 34 of 52 05965-014 CHA TO CHD 14-BIT SERIAL LVDS HSC-ADC-FPGA HIGH SPEED DESERIALIZATION BOARD 2 CH 14-BIT PARALLEL CMOS SPI HSC-ADC-EVALA-DC FIFO DATA CAPTURE BOARD USB CONNECTION PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE AD9259 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9259 Rev. A evaluation board. * POWER: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P503. AIN: The evaluation board is set up for a transformercoupled analog input with optimum 50 impedance matching out to 200 MHz (see Figure 62). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2. 0 -2 -4 AMPLITUDE (dBFS) 50 terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U202). Simply populate R225 and R227 with 0 resistors and remove R217 and R218 to disconnect the default clock path inputs. In addition, populate C207 and C208 with a 0.1 F capacitor and remove C210 and C211 to disconnect the default cloth path outputs. The AD9515 has many pin-strappable options that are set to a default working condition. Consult the AD9515 data sheet for more information about these and other options. If using an oscillator, two oscillator footprint options are also available (OSC201) to check the ADC performance. J205 gives the user flexibility in using the enable pin, which is common on most oscillators. * * PDWN: To enable the power-down feature, simply short J201 to the on position (AVDD) on the PDWN pin. SCLK/DTP: To enable the digital test pattern on the digital outputs of the ADC, use J204. If J204 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 0000 will be enabled. See the SCLK/DTP Pin section for details. SDIO/ODM: To enable the low power, reduced signal option similar to the IEEE 1595.3 reduced range link LVDS output standard, use J203. If J203 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, which reduces the power of the DRVDD supply. See the SDIO/ODM Pin section for more details. CSB: To enable the SPI information on the SDIO and SCLK pins that is to be processed, simply tie J202 low in the always enable mode. To ignore the SDIO and SCLK information, tie J202 to AVDD. Non-SPI Mode: For users who wish to operate the DUT without using SPI, simply remove the J202, J203, and J204 jumpers. This disconnects the CSB, SCLK/DTP, and SDIO/ OMD pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. D+, D-: If an alternative data capture method to the setup described in Figure 61 is used, optional receiver terminations, R206 to R211, can be installed next to the high speed backplane connector. * -3dB CUTOFF = 200MHz -6 -8 -10 -12 05965-088 -14 -16 * 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 62. Evaluation Board Full Power Bandwidth * VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R237. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Simply populate R231 and R235 and remove C214. Proper use of the VREF options is noted in the Voltage Reference section. RBIAS: RBIAS has a default setting of 10 k (R201) to ground and is used to set the ADC core bias current. To further lower the core power (excluding the LVDS driver supply), simply change the resistor setting. However, performance of the ADC will degrade depending on the resistor chosen. See the RBIAS Pin section for more information. CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input is * * * * * Rev. 0 | Page 35 of 52 AD9259 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this particular drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 16. For more details on the AD8332 dual VGA, including how it works and its optional pin settings, consult the AD8332 data sheet. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. * * * Remove R102, R115, R128, R141, T101, T102, T103, and T104 in the default analog input path. Populate R101, R114, R127, and R140 with 0 resistors in the analog input path. Populate R106, R107, R119, R120, R132, R133, R144, and R145 with 10 k resistors to provide an input commonmode level to the analog input. Populate R105, R113, R118, R124, R131, R137, R151, and R160 with 0 resistors in the analog input path. * Currently, L301 to L308 and L401 to L408 are populated with 0 resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary. Rev. 0 | Page 36 of 52 AD9259 AVDD_DUT R105 DNP FB102 R108 10 33 R106 DNP CM1 2 3 5 4 CH_A P102 VGA INPUT CONNECTION DNP INH1 AIN CHANNEL A R101 P101 DNP AIN R103 R102 0 64.9 R104 0 C101 0.1F R152 DNP T101 1 6 VIN_A R161 499 C103 DNP C104 2.2pF R109 1k VIN_A FB103 R110 33 10 C105 DNP R156 DNP CM1 R107 DNP R113 FB101 DNP 10 C102 0.1F CH_A CM1 E101 AVDD_DUT R111 1k R112 1k C107 0.1F C106 DNP AVDD_DUT AVDD_DUT VGA INPUT CONNECTION INH2 CHANNEL B R114 P103 DNP AIN R115 64.9 P104 DNP AIN R117 0 CH_B R118 DNP FB105 R121 10 33 R119 DNP R153 DNP T102 1 6 FB104 10 C108 0.1F CM2 R116 0 VIN_B R162 499 C110 DNP C111 2.2pF R123 1k VIN_B FB106 R122 33 10 C112 DNP R157 DNP 2 3 5 4 CM2 R120 DNP R124 C109 DNP 0.1F CH_B CM2 E102 AVDD_DUT R125 1k R126 1k C114 0.1F C113 DNP AVDD_DUT R154 DNP AVDD_DUT CH_C P106 VGA INPUT CONNECTION DNP INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0 64.9 R130 0 C115 0.1F R131 DNP FB108 R134 10 33 R132 DNP T103 1 6 VIN_C R163 499 C117 DNP C118 2.2pF R135 1k VIN_C R158 DNP CM3 2 3 5 4 CM3 R133 DNP R137 FB107 DNP 10 C116 0.1F CH_C CM3 E103 FB109 R136 33 10 C120 DNP C119 DNP AVDD_DUT R138 1k R139 1k C121 0.1F AVDD_DUT AVDD_DUT VGA INPUT CONNECTION INH4 CHANNEL D R140 P107 DNP AIN R141 64.9 P108 DNP AIN R142 0 CH_D R151 DNP FB111 R146 10 33 R144 DNP R155 DNP T104 1 6 FB110 C122 10 0.1F VIN_D R164 499 C124 DNP C125 2.2pF R148 1k VIN_D FB112 R147 33 10 C126 DNP R159 DNP CM4 2 3 5 4 CM4 R145 DNP R160 R143 DNP 0 C123 0.1F CH_D CM4 E104 AVDD_DUT DNP: DO NOT POPULATE Figure 63. Evaluation Board Schematic, DUT Analog Inputs Rev. 0 | Page 37 of 52 05965-015 R149 1k R150 1k C128 0.1F C127 DNP AVDD_DUT AD9259 REFERENCE CIRCUIT OPTIONAL EXT REF AVDD_DUT R229 4.99k R231 DNP R234 DNP DNP VREF = 0.5V 60 P202 GNDCD10 C10 GNDCD9 C204 0.1F REFERENCE DECOUPLING U203 ADR510/20 1V VOUT TRIM/NC VREF_DUT VREF SELECT VSENSE_DUT DIGITAL OUTPUTS GND DNP DNP VREF = EXTERNAL DCO 40 59 39 58 38 57 37 56 CHC 36 55 CHD 1 3 J201 35 54 34 53 33 R246 DNP R248 DNP R250 DNP R252 DNP R254 DNP R251 0 R253 0 R255 0 R249 0 R247 0 R256 DNP R258 DNP AVDD_3.3V S7 R260 DNP AVDD_3.3V S8 AVDD_3.3V S9 R262 DNP R264 DNP AVDD_3.3V S10 AVDD_3.3V S5 R257 0 R259 0 R261 0 R263 0 R265 0 C8 C7 C6 C5 C4 C3 C9 GNDCD8 R232 DNP R235 DNP D10 D9 D8 GNDCD7 C202 2.2F C203 0.1F AVDD_DUT 50 49 48 GNDCD6 R201 10k R228 470k C213 0.1F R233 DNP R237 0 VREF = 1V CHA CHB C212 0.1F C214 1F DNP VREF = 0.5V(1+R232/R233) FCO R230 10k R236 DNP DCO R206 DNP R207 FCO DNP CHA R208 DNP D7 D6 47 CHB R209 DNP CW AVDD_DUT AVDD_DUT VIN_C VIN_C VREF_DUT VSENSE_DUT AVDD_DUT VIN_B VIN_B C201 0.1F U201 48 47 46 45 44 43 42 41 40 39 38 37 AVDD_DUT REMOVE C214 WHEN USING EXTERNAL VREF VIN-C VIN+C AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD VIN+B VIN-B GNDCD5 46 GNDCD4 R202 100k CHC R210 DNP D5 45 GNDCD3 CHD R211 DNP D4 44 GNDCD2 PWDN ENABLE ALWAYS ENABLE SPI AVDD_3.3V S0 AVDD_3.3V S1 AVDD_3.3V S2 R244 DNP R245 0 2 AVDD_DUT AVDD_DUT VIN_A VIN_A AVDD_DUT R266 100k - DNP R267 100k - DNP AD9259 LFCSP AVDD AVDD VIN-A VIN+A AVDD PDWN 1 3 J202 2 ODM ENABLE CSB_DUT D3 43 52 32 C2GNDCD1 D2 42 D-D D+D D-C D+C D-B D+B D-A D+A FCO- FCO+ DCO- DCO+ R203 100k R204 100k R205 10k AVDD_DUT AVDD_DUT VIN_D VIN_D AVDD_DUT AVDD_DUT CLK CLK AVDD_DUT AVDD_DUT DRVDD_DUT GND CSB SDIO/ODM SCLK/DTP AVDD DRVDD DRGND 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 AVDD AVDD VIN-D VIN+D AVDD AVDD CLK- CLK+ AVDD AVDD DRVDD DRGND AVDD_DUT DRVDD_DUT GND DTP ENABLE J203 1 3 SDIO_ODM J204 3 1 SCLK_DTP 2 AVDD_3.3V S6 2 13 14 15 16 17 18 19 20 21 22 23 24 51 D1 41 C1 31 GNDAB10 30 C10 B10 20 10 GNDAB9 29 9 28 8 27 7 26 6 SCLK_CHB SDI_CHB 25 5 24 A9 GNDAB8 CHD CHD CHC CHC CHB CHB CHA CHA FCO FCO DCO DCO AVDD_3.3V S3 AVDD_3.3V S4 B9 A8 A7 A6 A5 A4 CLK CSB3__CHB 4 23 LVPECL OUTPUT 3 22 A3 B8 GNDAB7 19 18 B7 GNDAB6 R220 DNP R221 10k U202 33 RSET 32 GND 31 ENCODE INPUT OSC201 14 VCC OE 1 12 VCC' OE' 3 10 5 OUT' GND' 8 OUT GND 7 VS 1 6 7 8 9 10 11 12 13 14 15 16 25 ENC E201 1 R238 DNP R239 10k VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 ENC DNP 2 5 T201 3 4 CR201 HSMS2812 3 2 R216 0 C216 0.1F R218 0 C206 0.1F 1 6 1 Figure 64. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface Rev. 0 | Page 38 of 52 R214 10k 2 J205 ENABLE AVDD_3.3V OPTIONAL CLOCK DRIVE CIRCUIT R222 4.02k AVDD_3.3V C207 0.1F DNP AVDD_3.3V C224 0.1F 17 GNDAB5 B6 B5 GNDAB4 OPTIONAL CLOCK OSCILLATOR 16 15 GNDAB3 AVDD_3.3V SCLK_CHA B4 B3 GNDAB2 14 13 SDI_CHA CSB1_CHA 1 GND_PAD OUT0 OUT0B DISABLE R219 R215 DNP 10k OPT_CLK 23 22 CB3LV-3C OPT_CLK R242 100 R225 0 DNP R226 49.9 DNP 2 CLK 3 CLKB AD9515 SIGNAL = AVDD_3.3V; 4, 17,20, 21, 24, 26, 29, 30 SIGNAL = DNC;27,28 C208 0.1F DNP CSB4_CHB CLK R240 243 OUT1 19 OUT1B 18 R241 243 1 R243 100 CLK C210 0.1F C209 0.1F DNP E202 LVDS OUTPUT 1 E203 C215 0.1F DNP CLIP SINE OUT (DEFAULT) CLK C217 0.1F C218 0.1F C219 0.1F C220 0.1F C221 0.1F AVDD_3.3V SDO_CHB 2 21 1 A2 A1 GNDAB1 B2 B1 12 11 CSB2_CHA SDO_CHA R212 0 DNP 5 SYNCB P201 OPT_CLK R227 0 DNP NC = NO CONNECT HEADERM1469169_1 CLOCK CIRCUIT R213 49.9k C205 0.1F R205 TO R211 OPTIONAL OUTPUT TERMINATIONS P203 OPT_CLK R217 0 R223 0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 C222 0.1F C223 0.1F R224 0 DNP: DO NOT POPULATE C211 0.1F 05965-016 AD9259 POPULATE L301 TO L308 WITH 0 RESISTORS OR DESIGN YOUR OWN FILTER. CH_D CH_D CH_C R301 DNP C301 L301 DNP 0 R302 DNP C302 L302 L303 DNP L304 0 0 0 C304 DNP L308 0 R304 DNP C308 0.1F C309 1000pF R310 187 CH_C EXTERNAL VARIABLE GAIN DRIVE VG VARIABLE GAIN CIRCUIT (0V TO 1.0V DC) VG GND CW AVDD_5V R320 R319 39k 10k 1 2 JP301 POWER DOWN ENABLE (0V TO 1V = DISABLE POWER) C303 L305 DNP 0 R303 DNP C305 0.1F R305 374 R307 187 U301 25 26 27 28 29 30 31 32 ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 R308 187 L306 L307 0 0 OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS C AND D AVDD_5V R306 374 R309 187 AVDD_5V VOL1 VPSV AD8332 LMD1 LMD2 LON1 VPS1 INH1 C312 0.1F INH2 VPS2 LON2 C311 0.1F C313 0.1F C314 0.1F R315 10k C315 10F C316 0.1F R316 274 C317 0.018F C320 0.1F C321 0.1F R317 274 C322 0.018F C325 0.1F C326 10F R318 10k C318 22pF L309 120nH C319 0.1F C323 22pF L310 120nH C324 0.1F INH3 05965-017 DNP: DO NOT POPULATE INH4 Figure 65. Evaluation Board Schematic, Optional DUT Analog Input Drive Rev. 0 | Page 39 of 52 MODE PIN POSITIVE GAIN SLOPE = 0V TO 1.0V NEGATIVE GAIN SLOPE = 2.25V TO 5.0V HILO PIN HI GAIN RANGE = 2.25V TO 5.0V LO GAIN RANGE = 0V TO 1.0V R313 10k DNP VOL2 VOH2 COMM COMM VOH1 NC R312 10k AVDD_5V C310 0.1F R311 10k DNP RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 16 15 14 13 12 11 10 9 VG R314 10k DNP 1 2 3 4 5 AVDD_5V AVDD_5V 6 7 8 RCLAMP PIN HILO PIN = LO = 50mV HILO PIN = H = 75mV C306 C307 0.1F 0.1F 24 23 22 21 20 19 18 17 AD9259 CH_B CH_B CH_A R401 DNP C401 L401 DNP 0 SPI CIRCUITRY FROM FIFO +5V = PROGRAMMING = AVDD_5V +3.3V = NORMAL OPERATION = AVDD_3.3V AVDD_3.3V AVDD_5V J402 C402 L402 L403 DNP L404 0 0 0 R402 DNP POWER DOWN ENABLE (0V TO 1V = DISABLE POWER) POPULATE L401 TO L408 WITH 0 RESISTORS OR DESIGN YOUR OWN FILTER. C403 L405 DNP 0 R403 DNP L406 L407 0 0 C404 DNP L408 0 R404 DNP CH_A CSB1_CHA SCLK_CHA SDI_CHA C405 0.1F C406 C407 0.1F 0.1F R426 0 R428 0 R420 0 AVDD_5V R407 187 R410 187 U402 1 VDD 2 GP5 3 GP4 4 R422 0, DNP 8 VSS 7 GP0 6 GP1 R421 0, DNP R408 187 R409 187 C412 0.1F C427 0.1F R427 0 R405 374 C411 1000pF R413 10k DNP R406 374 C408 0.1F SDO_CHA REMOVE WHEN USING OR PROGRAMMING PIC (U402) AVDD_3.3V 24 23 22 21 20 AVDD_5V NC AVDD_5V RCLAMP PIN HILO PIN = LO = 50mV HILO PIN = H = 75mV R411 10k U401 19 18 17 R433 1k COMM VOH1 VOL1 VPSV VOL2 VOH2 COMM R412 10k DNP VG RESET/REPROGRAM R424 10k DNP 1 2 3 4 MCLR/ GP2 5 GP3 PIC12F629 R419 261 CR401 R418 4.75k S401 R423 0, DNP SDIO_ODM AVDD_DUT R431 1k R425 10k 2 GND 3 A2 VCC 5 Y2 4 AVDD_DUT OPTIONAL LON1 VPS1 INH1 LMD1 LMD2 1 2 3 4 5 C410 0.1F 6 7 8 INH2 VPS2 LON2 OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS A AND B HILO PIN HI GAIN RANGE = 2.25V-5.0V LO GAIN RANGE = 0V TO 1.0V AVDD_5V AVDD_5V MODE PIN POSITIVE GAIN SLOPE = 0V TO 1.0V NEGATIVE GAIN SLOPE = 2.25V-5.0V R416 C420 0.018F 274 Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface (Continued) AD8332 C423 0.1F ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 16 15 14 13 12 11 10 9 C424 0.1F RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 R432 NC7WZ07 1k 1 A1 Y1 6 Rev. 0 | Page 40 of 52 E401 C409 0.1F 25 26 27 28 29 30 31 32 U403 C429 0.1F MCLR/GP3 J401 PICVCC 1 2 GP1 3 4 GP0 5 6 R414 10k C426 R417 10F 10k C413 10F C414 0.1F R415 274 C416 0.1F C417 0.1F C425 0.1F C415 0.018F NC7WZ16 1 A1 Y1 6 7 8 9 10 2 GND 3 A2 R430 10k R429 10k VCC 5 Y2 4 SCLK_DTP AVDD_DUT CSB_DUT GP1 GP0 PICVCC MCLR/GP3 PIC PROGRAMMING HEADER C418 22pF L409 120nH L410 120nH C422 0.1F INH1 DNP: DO NOT POPULATE C419 0.1F C421 22pF U404 C428 0.1F INH2 05965-018 POWER SUPPLY INPUT 6V, 2V MAXIMUM F501 FER501 1 4 3 CHOKE_COIL CR501 R501 261 2 PWR_IN SMDC110F + 2 3 C501 10F D501 S2A_RECT 2A DO-214AA P503 1 D502 3A SHOT_RECT DO-214AB OPTIONAL POWER INPUT P501 P1 1 5V_AVDD AVDD_5V +5.0V C518 0.1F C519 0.1F AVDD_5V C520 0.1F C502 10F C503 0.1F L502 10H AVDD_DUT C504 10F C505 0.1F L508 10H AVDD_3.3V C508 10F C509 0.1F +3.3V AVDD_3.3V C524 0.1F C525 0.1F C526 0.1F +1.8V AVDD_DUT C527 0.1F C528 0.1F DUT_AVDD 3.3V_AVDD DUT_DRVDD P2 2 P3 3 P4 4 P5 5 P6 6 P7 7 P8 8 L503 10H DECOUPLING CAPACITORS C521 0.1F C522 0.1F C523 0.1F C529 0.1F C530 0.1F C531 0.1F GND C514 1F 1 U503 PWR_IN INPUT C512 1F DNP: DO NOT POPULATE 05965-019 U504 L504 10H 2 4 DUT_DRVDD PWR_IN 3 ADP33339AKC-5 INPUT OUTPUT1 2 3 ADP33339AKC-1.8 OUTPUT1 1 C515 1F C532 1F GND GND 1 1 C513 1F C534 1F GND Figure 67. Evaluation Board Schematic, Power Supply Inputs Rev. 0 | Page 41 of 52 L501 10H DRVDD_DUT +1.8V DRVDD_DUT C506 10F C507 0.1F U501 PWR_IN INPUT OUTPUT4 4 3 OUTPUT1 ADP33339AKC-1.8 2 L505 10H DUT_AVDD PWR_IN 3 OUTPUT4 H1 H3 C516 0.1F C517 0.1F H2 H4 MOUNTING HOLES CONNECTED TO GROUND U502 ADP33339AKC-3.3 INPUT OUTPUT1 2 OUTPUT4 4 L506 10H 3.3V_AVDD C533 1F L507 10H 5V_AVDD OUTPUT4 4 C535 1F AD9259 AD9259 Figure 68. Evaluation Board Layout, Primary Side Rev. 0 | Page 42 of 52 05965-020 AD9259 Figure 69. Evaluation Board Layout, Ground Plane Rev. 0 | Page 43 of 52 05965-021 AD9259 Figure 70. Evaluation Board Layout, Power Plane Rev. 0 | Page 44 of 52 05965-022 AD9259 Figure 71. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. 0 | Page 45 of 52 05965-023 AD9259 Table 16. Evaluation Board Bill of Materials (BOM) Qnty. per Board 1 75 Item 1 2 3 4 REFDES AD9259LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, C218, C219, C220, C221, C222, C223, C224, C310, C311, C312, C313, C314, C316, C319, C320, C321, C324, C325, C409, C410, C412, C414, C416, C417, C419, C422, C423, C424, C425, C427, C428, C429, C503, C505, C507, C509, C516, C517, C518, C519, C520, C521, C522, C523, C524, C525, C526, C527, C528, C529, C530, C531 C104, C111, C118, C125 C315, C326, C413, C426 C202 C309, C411 C317, C322, C415, C420 C318, C323, C418, C421 C501 C214, C512, C513, C514, C515, C532, C533, C534, C535 C305, C306, C307, C308, C405, C406, C407, C408 C502, C504, C506, C508 CR201 CR401, CR501 D502 D501 Device PCB Capacitor Pkg. PCB 402 Value PCB 0.1 F, ceramic, X5R, 10 V, 10% tol Mfg. Panasonic Mfg. Part Number ECJ-0EB1A104K Capacitor 402 4 5 6 7 8 9 10 4 1 2 4 4 1 9 Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor 805 603 402 402 402 1206 603 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V 10 F, 6.3 V 10% ceramic, X5R 2.2 F, ceramic, X5R, 6.3 V, 10% tol 1000 pF, ceramic, X7R, 25 V, 10% tol 0.018 F, ceramic, X7R, 16 V, 10% tol 22 pF, ceramic, NPO, 5% tol, 50 V 10 F, tantalum, 16 V, 20% tol 1 F, ceramic, X5R, 6.3 V, 10% tol 0.1 F, ceramic, X7R, 50 V, 10% tol 10 F, ceramic, X5R, 6.3 V, 20% tol 30 V, 20 mA, dual Schottky Green, 4 V, 5 m candela 3 A, 30 V, SMC 2 A, 50 V, SMC Murata GRM1555C1H2R2GZ01B AVX Panasonic Kemet AVX Kemet Rohm Panasonic 08056D106KAT2A ECJ-1VB0J225K C0402C102K3RACTU 0402YC183KAT2A C0402C220J5GACTU TCA1C106M8R ECJ-1VB0J105K 11 8 Capacitor 805 AVX 08055C104KAT2A 12 13 14 15 16 4 1 2 1 1 Capacitor Diode LED Diode Diode 603 SOT-23 603 DO-214AB DO-214AA Panasonic Agilent Technologies Panasonic Micro Commercial Co. Micro Commercial Co. ECJ-1VB0J106M HSMS2812 LNJ306G8TRA SK33MSCT S2A Rev. 0 | Page 46 of 52 AD9259 Item 17 Qnty. per Board 1 REFDES F501 Device Fuse Pkg. 1210 Value 6.0 V, 2.2 A tripcurrent resettable fuse 10 H, 5 A, 50 V, 190 @ 100 MHz 10 , test freq 100 MHz, 25% tol, 500 mA 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin 100 mil header male, 4 x 3 triple row straight 100 mil header, male, 2 x 5 double row straight 10 H, bead core 3.2 x 2.5 x 1.6 SMD, 2 A 120 nH, test freq 100 MHz, 5% tol, 150 mA 0 , 1/8 W, 5% tol Mfg. Tyco/Raychem Mfg. Part Number NANOSMDC110F-2 18 19 1 12 FER501 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 JP301 J205, J402 J201 to J204 Choke Coil Ferrite bead 2020 603 Murata Murata DLW5BSN191SQ2L BLM18BA100SN1 20 21 22 1 2 1 Connector Connector Connector 2-pin 3-pin 12-pin Samtec Samtec Samtec TSW-102-07-G-S TSW-103-07-G-S TSW-104-08-G-T 23 1 J401 Connector 10-pin Samtec TSW-105-08-G-D 24 8 L501, L502, L503, L504, L505, L506, L507, L508 L309, L310, L409, L410 Ferrite bead 1210 Panasonic-ECG EXC-CL3225U1 25 4 Inductor 402 Murata LQG15HNR12J02B 26 16 27 28 1 5 L301, L302, L303, L304, L305, L306, L307, L308, L401, L402, L403, L404, L405, L406, L407, L408 OSC201 P101, P103, P105, P107, P201 P202 Resistor 805 Panasonic ERJ-6GEY0R00V Oscillator Connector SMT SMA 29 1 Connector HEADER 30 31 1 15 P503 R201, R205, R214, R215, R221, R239, R312, R315, R318, R411, R414, R417, R425, R429, R430 R103, R117, R129, R142, R216, R217, R218, R223, R224, R237, R420, R426, R427, R428 R102, R115, R128, R141 R104, R116, R130, R143 Connector Resistor 0.1", PCMT 402 Clock oscillator, 50.00 MHz, 3.3 V Side-mount SMA for 0.063" board thickness 1469169-1, right angle 2-pair, 25 mm, header assembly RAPC722, power supply connector 10 k, 1/16 W, 5% tol CTS REEVES Johnson Components Tyco CB3LV-3C-50M0000-T 142-0711-821 1469169-1 Switchcraft Panasonic SC1153 ERJ-2GEJ103X 32 14 Resistor 402 0 , 1/16 W, 5% tol Panasonic ERJ-2GE0R00X 33 34 4 4 Resistor Resistor 402 603 64.9 , 1/16 W, 1% tol 0 , 1/10 W, 5% tol Panasonic Panasonic ERJ-2RKF64R9X ERJ-3GEY0R00V Rev. 0 | Page 47 of 52 AD9259 Item 35 Qnty. per Board 15 REFDES R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433 R108, R110, R121, R122, R134, R136, R146, R147 R161, R162, R163, R164 R202, R203, R204 R222 R213 R229 R230, R319 Device Resistor Pkg. 402 Value 1 k, 1/16 W, 1% tol Mfg. Panasonic Mfg. Part Number ERJ-2RKF1001X 36 8 Resistor 402 33 , 1/16 W, 5% tol 499 , 1/16 W, 1% tol 100 k, 1/16 W, 1% tol 4.02 k, 1/16 W, 1% tol 49.9 , 1/16 W, 0.5% tol 4.99 k, 1/16 W, 5% tol 10 k, Cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 W 470 k, 1/16 W, 5% tol 39 k, 1/16 W, 5% tol 187 , 1/16 W, 1% tol 374 , 1/16 W, 1% tol 274 , 1/16 W, 1% tol 0 , 1/20 W, 5% tol Panasonic ERJ-2GEJ330X 37 38 39 40 41 42 4 3 1 1 1 2 Resistor Resistor Resistor Resistor Resistor Potentiometer 402 402 402 402 402 3-lead Panasonic Panasonic Panasonic Susumu Panasonic BC Components ERJ-2RKF4990X ERJ-2RKF1003X ERJ-2RKF4021X RR0510R-49R9-D ERJ-2RKF4991X CT-94W-103 43 44 45 1 1 8 R228 R320 R307, R308, R309, R310, R407, R408, R409, R410 R305, R306, R405, R406 R316, R317, R415, R416 R245, R247, R249, R251, R253, R255, R257, R259, R261, R263, R265 R418 R419 R501 R240, R241 R242, R243 S401 T101, T102, T103, T104, T201 U501, U503 Resistor Resistor Resistor 402 402 402 Yageo America Susumu Panasonic 9C04021A4703JLHF3 RR0510P-393-D ERJ-2RKF1870X 46 47 48 4 4 11 Resistor Resistor Resistor 402 402 201 Panasonic Panasonic Panasonic ERJ-2RKF3740X ERJ-2RKF2740X ERJ-1GE0R00C 49 50 51 52 53 54 55 4 1 1 2 2 1 5 Resistor Resistor Resistor Resistor Resistor Switch Transformer 402 402 603 402 402 SMD CD542 56 2 IC SOT-223 4.75 k, 1/16 W, 1% tol 261 , 1/16 W, 1% tol 261 , 1/16 W, 1% tol 243 , 1/16 W, 1% tol 100 , 1/16 W, 1% tol LIGHT TOUCH, 100GE, 5 mm ADT1-1WT, 1:1 impedance ratio transformer ADP33339AKC-1.8, 1.5 A, 1.8 V LDO regulator Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Mini-Circuits ERJ-2RKF4751X ERJ-2RKF2610X ERJ-3EKF2610V ERJ-2RKF2430X ERJ-2RKF1000X EVQ-PLDA15 ADT1-1WT ADI ADP33339AKC-1.8 Rev. 0 | Page 48 of 52 AD9259 Item 57 Qnty. per Board 2 REFDES U301, U401 Device IC Pkg. LFCSP, CP-32 Value AD8332ACP, ultralow noise precision dual VGA ADP33339AKC-5 ADP33339AKC-3.3 AD9259-50, quad, 14-bit, 50 MSPS serial LVDS 1.8 V ADC ADR510AR, 1.0 V, precision low noise shunt voltage reference AD9515 NC7WZ07 NC7WZ16 Flash prog mem 1kx14, RAM size 64 x 8, 20 MHz speed, PIC12F controller series Mfg. ADI Mfg. Part Number AD8332ACP 58 59 60 1 1 1 U504 U502 U201 IC IC IC SOT-223 SOT-223 LFCSP, CP-48-1 ADI ADI ADI ADP33339AKC-5 ADP33339AKC-3.3 AD9259BCPZ-50 61 1 U203 IC SOT-23 ADI ADR510AR 62 63 64 65 1 1 1 1 U202 U403 U404 U402 IC IC IC IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC ADI Fairchild Fairchild Microchip AD9515BCPZ NC7WZ07P6X NC7WZ16P6X PIC12F629-I/SN Rev. 0 | Page 49 of 52 AD9259 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 0.30 0.23 0.18 48 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 6.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 5.25 5.10 SQ 4.95 0.50 0.40 0.30 25 24 12 13 0.25 MIN 5.50 REF 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 72. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9259BCPZ-50 1 AD9259BCPZRL-501 AD9259-50EB 1 Temperature Range -40C to +85C -40C to +85C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel Evaluation Board Package Option CP-48-1 CP-48-1 Z = Pb-free part. Rev. 0 | Page 50 of 52 AD9259 NOTES Rev. 0 | Page 51 of 52 AD9259 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05965-0-6/06(0) Rev. 0 | Page 52 of 52 |
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